1. Field of the Invention
The present invention relates to a disk array controller comprising a plurality of central processing units (CPUs) for controlling the interface between a host computer or disk device(s), and a plurality of memories for storing the control data.
2. Description of Related Art
A structure of a disk array controller of the conventional art utilizing a shared memory multiprocessor system is shown in FIG. 21. In the controller shown in FIG. 21, a plurality of CPU-PK (packages) 2101, a shared memory package (SM-PK) #A 2103 equipped with the shared memory for storing control data, and a shared memory package (SM-PK) #B 2104 are connected by way of the shared memory path 2102. Each CPU-PK is connected to either the host computer or the disk device. Each CPU-PK contains a plurality of CPUs and each CPU performs transfer of data from the host computer or disk device, or controls the transfer of data to the host computer or disk device by utilizing the control data stored in the shared memory.
The memory controller of the conventional art has a plurality of paths connecting between a plurality of central processing units (CPU) and memories in order to shorten the response time for memory access and increase the number of processable transactions. In order to increase the number of processable transactions, the processable transactions must be optimally distributed along the plurality of paths. A technology for distributing the transactions is disclosed in Japanese Published Unexamined Patent Application No. 9-146863 for distributing transactions by checking flags indicating the use or non-use of a path.
Another method is known in the memory controller of the conventional art for improving reliability by duplication of paths and duplication of the memory. Such a memory controller device is for instance, disclosed in Japanese Published Unexamined Patent Application No. 9-325916 and utilizes two paths for memory access to increase the number of processable transactions and at the same time increase reliability of the data by dual writing of important data onto two memories. In this kind of method however, in order to write the same data on a plurality of non-synchronous memories, problems such as data mismatches or deadlocks may occur when simultaneously attempting a plurality of dual writing. In this kind of dual write, simplifying of the access paths and elimination of the data mismatch or deadlock problems was attempted by establishing fixed buses for use by each memory address.
However, in this method, the response time during serial processing on the bus becomes a problem when multiple accesses occur, and performance bottlenecks relating to the number of processable transactions are also a disadvantage. Also, in spite of the duplication of buses, all the connected central processing units (CPU) are affected when a problem occurs on a bus.
In an attempt to improve both performance and reliability, the star connection which connects the CPU and memory in a ratio of one to one was contrived. In the method disclosed in Japanese Published Unexamined Patent Application No. 58-16362 each duplicated memory from each CPU is connected by one bus line each. In this method, an increased number of paths can be simultaneously accessed compared to the above methods, and the number of processable transactions can be further increased. Each CPU is connected to a path so that compared to the above methods, the range of CPU likely to be affected by a problem on one path is limited and the reliability is also high. Still further in this technology, interfaces are provided between the shared memories in order to avoid problems during dual write processing such as deadlocks or data mismatches.
The shared memory in the disk array controller does not require data transfer in as large amounts as the cache memory, however increasing the number of transactions and shortening the response time for each data transfer is necessary. A one-to-one connection between each CPU and the shared memory is therefore suitable as disclosed in the technology of Japanese Published Unexamined Patent Application No. 58-16362.
The transfer of large quantities of data at high speed however, is necessary between each CPU and cache memory so that increasing the number of access paths is required. Establishing connections in a ratio of one to one between each CPU and memory is therefore a suitable method as disclosed in Japanese Published Unexamined Patent Application No. 58-16362.
However, as previously mentioned, there is a physical limit on how many connectors can be mounted on the package comprising the cache memory or how many pins can be mounted on the LSI comprising each memory. This physical limit on the amount of hardware also limits an increase in the number of access paths that can be installed between each CPU and shared memory.
As mentioned above, the star connection method is an excellent bus connection method for increasing the number of processable transactions and improving reliability. The technology disclosed in Japanese Published Unexamined Patent Application No. 58-16362 however has the disadvantage that since an interface connects with the shared memory for dual write, the entire shared memory becomes unusable in the event a problem occurs on this interface. Also, since both of the shared memories lock up during dual write, other access is refused, creating the problem that the number of processable transactions decreases. Further, even if simply increasing the number of paths is attempted, serial processing of dual write must be performed just as with the previously related method, so that a significant increase in the number of transactions cannot be achieved. One path connects between each CPU and shared memory so that accessing data might become impossible if a problem occurs on that path.
Whereupon, it is therefore an object of this invention to provide a disk array controller having a shorter memory access response time between a plurality of CPUs and duplicated memories, and further capable of an increased number of processable transactions.
Another object of this invention is to provide a selection control means to select a path that will not cause data mismatches or deadlocks during dual write.
In order to resolve the above mentioned problems, this invention is installed with a path lock table to indicate the usage status of each path on the shared memory path interface for connecting and controlling the CPU and each memory path, and is further installed with a memory lock table indicating memory lock information for the shared memory control circuit for connecting and controlling the shared memory and each memory path. In processing (single read, single write, atomic modify) for other than dual write, the number of waiting transactions (transactions awaiting processing) on each path is shown, and a path with a short path queue length selected. In processing for dual write and dual write atomic modify, the path lock table is referred to when selecting the path, and if the number of dual write transactions already being processed is less than a fixed number, then dual write processing starts, and if greater than a fixed number, then dual write processing sets to standby. Further, when selecting a path for dual write, paths are selected that are different from those paths where dual write processing is already being performed.